Many electrical circuits use amplifiers, which amplify one or more input voltages according to a gain setting of the amplifier. One particular type of amplifier is a difference amplifier that accepts two input voltages and supplies an output voltage that is a function of the gain setting of the amplifier and the difference between the two input voltages. A selectable-gain amplifier permits a user to select the gain of the amplifier by use of external components or provision of external signals.
FIG. 1A illustrates a prior art circuit having three gain channels, the gains of which are binary weighted. In FIG. 1A, each gain channel has switch SWx that connects input voltage VIN to the gain channel when the switch is closed. Amplifier 10A comprises amplification element 12 (e.g., an operational amplifier) having non-inverting input 14 and inverting input 16. Gain resistors RM1, RM2 and RM4 are electrically coupled between inverting input 16 and input voltage VIN when switches SW1, SW2 and SW4 are closed respectively. Gain resistors RM1, RM2 and RM4 respectively correspond to gain channels having gains of 1×, 2× and 4×. Feedback resistor RFM is connected between inverting input 16 and output node 18. Non-inverting input 14 of amplification element 12 is connected to analog ground. Because the gain channels and feedback resistor RFM are coupled to inverting input 16, amplifier 10A provides inverting gains. To provide binary weighted gains, the nominal resistances of the resistors in amplifier 10A may be chosen so that (1) resistors RFM and RM1 have the same nominal resistances, (2) resistor RM2 has half the nominal resistance of resistor RFM or RM1, and (3) resistor RM4 has one-fourth the nominal resistance of resistor RFM or RM1.
To configure amplifier 10A with a gain of 1×, SW1 is closed, while switches SW2 and SW4 are left open. Likewise, to configure amplifier 10A with a gain of 2×, SW2 is closed, while switches SW1 and SW4 are left open. Similarly, to configure amplifier 10A with a gain of 4×, SW4 is closed, while switches SW1 and SW2 are left open. Switches SW1, SW2 and SW4 are opened and closed responsive to digital signals.
Amplifier 10A may be configured with additional gains by coupling the gain channels in a manner that adds the gain values of the gain channels. Specifically, the gains are added by closing two or more switches SW1, SW2 and SW4, thereby connecting their respective gain channels together to input voltage VIN. For example, as shown in FIG. 1A, amplifier 10A is configured with a gain of 3× by closing switches SW1 and SW2, thereby connecting input voltage VIN to gain channels 1× and 2×. Table 1A provides a chart of connections to configure amplifier 10A with one of seven possible integer gains.
TABLE 1AGainSW1SW2SW4−1closedopenopen−2openclosedopen−3closedclosedopen−4openopenclosed−5closedopenclosed−6openclosedclosed−7closedclosedclosed
The disadvantage of amplifier 10A having binary weighted gains is that the amplifier can provide only 2n−1 different integer gains using n gain channels. Furthermore, because switches SW1, SW2 and SW4 open and close responsive to digital signals, amplifier 10A requires at least one extra input pin to receive the digital signals.
FIG. 1B illustrates a prior art circuit similar to that illustrated in FIG. 1A, the amplifier having three gain channels that are binary weighted. As shown in FIG. 1B, each gain channel has corresponding positive and negative input terminals Px and Mx. Amplifier 10B comprises amplification element 12 (e.g., an operational amplifier) having non-inverting input 14 and inverting input 16. Gain resistors RP1, RP2 and RP4 are coupled between non-inverting input 14 and positive input pins P1, P2 and P4 (respectively). Positive input pins P1, P2 and P4 respectively correspond to gain channels having gains of 1×, 2× and 4×. Reference resistor RFP is connected between non-inverting input 14 and reference voltage VREF. Gain resistors RM1, RM2 and RM4 are coupled between inverting input 16 and negative input pins M1, M2 and M4 (respectively). Negative input pins M1, M2 and M4 respectively correspond to gain channels having gains of 1×, 2× and 4×. Feedback resistor RFM is connected between inverting input 16 and output node 18. To provide binary weighted gains, the nominal resistances of the resistors in amplifier 10B may be chosen so that (1) resistors RFP, RFM, RP1 and RM1 have the same nominal resistances, (2) each resistor RP2 and RM2 has half the nominal resistance of resistors RFP, RFM, RP1 or RM1, and (3) each resistor RP4 and RM4 has one-fourth the nominal resistance of resistors RFP, RFM, RP1 or RM1.
To configure amplifier 10B with a gain of 1×, positive input voltage VINP should be connected to input pin P1 and negative input voltage VINM should be connected to input pin M1. Likewise, to configure amplifier 10B with a gain of 2×, positive and negative input voltages should be connected to input pins P2 and M2, respectively. Similarly, to configure amplifier 10B with a gain of 4×, positive and negative input voltages should be connected to input pins P4 and M4, respectively.
Amplifier 10B may be configured with additional gains by combining the analog inputs in a manner that adds the gain values of the gain channels. Specifically, the gains are added by connecting the positive inputs of the gain channels together to positive input voltage VINP and the negative inputs of the gain channels together to negative input voltage VINM. For example, as shown in FIG. 1B, amplifier 10B is configured with a gain of 3× by connecting (1) positive input voltage VINP to input pins P1 and P2, which respectively correspond to the positive inputs of gain channels 1× and 2×, and (2) negative input voltage VINM to input pins M1 and M2, which respectively correspond to the negative inputs of gain channels 1× and 2×. Table 1B provides a chart of connections to configure amplifier 10B with one of seven possible integer gains.
TABLE 1BGainP1P2P4M1M2M41VINPFloatFloatVINMFloatFloat2FloatVINPFloatFloatVINMFloat3VINPVINPFloatVINMVINMFloat4FloatFloatVINPFloatFloatVINM5VINPFloatVINPVINMFloatVINM6FloatVINPVINPFloatVINMVINM7VINPVINPVINPVINMVINMVINM
Similar to amplifier 10A of FIG. 1A, one disadvantage of amplifier 10B is that amplifier 10B can provide only 2n−1 different integer gains of the same polarity using n gain channels since its gain channels also are binary weighted.
Another prior art circuit that also employs a control input separate from the analog signal input(s) is one in which the control input operates to internally change the gains of the gain channels. An example of such a prior art circuit is a digitally-controlled, variable-gain amplifier. The disadvantages of such a prior art amplifier are that (1) a separate control signal is required, and (2) the precision of the gain channels may degrade when the gain value of the gain channel is changed.
In view of the foregoing, it would be desirable to provide methods and circuits for increasing the number of selectable gain settings of an amplifier, as compared to that of a binary weighted amplifier, without increasing the number of gain channels.
It also would be desirable to provide methods and circuits for increasing the number of selectable gain settings of an amplifier without requiring use of a separate control signal.